RISC-V and the Open Architecture Moment in AI Chips

In May 2021, Nvidia announced an agreement to acquire Arm Holdings from SoftBank for $40 billion. The deal would have given Nvidia ownership of the instruction set architecture used in virtually every smartphone, tablet, and embedded processor on the planet. The response from the semiconductor industry was immediate and alarmed: Qualcomm, MediaTek, Apple, Google, and dozens of other Arm licensees issued statements expressing concern about the implications of their instruction set architecture being owned by a competitor.

The deal collapsed in February 2022 under regulatory pressure. But the episode clarified something important for every company that builds chips: depending on an architecture controlled by someone else introduces strategic risk that scales with your dependence. Arm’s IPO in 2023, which valued the company at $54 billion, removed the Nvidia-specific risk but did not remove the licensing fee risk or the strategic alignment risk. The moment Arm changes its licensing terms, every Arm licensee faces a renegotiation.

RISC-V, the open standard instruction set architecture developed at Berkeley beginning in 2010 and placed in the public domain through the RISC-V International consortium, is the hedge against this risk that an increasing number of AI chip designers are taking.

What RISC-V Actually Is

RISC-V (pronounced “risk five”) is a specification, not a chip. It defines a base integer instruction set and a set of standard extensions (for multiplication, floating point, vector operations, and more), with the crucial property that no one owns it. Anyone can implement RISC-V in silicon without paying royalties, without signing a license agreement, without concern that the specification will be changed to favor a competitor.

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The base ISA is small — the RV32I base integer instruction set has 47 instructions, compared to x86’s approximately 1,000+ instructions and Arm’s several hundred. This simplicity is a feature: a small, clean ISA is easier to implement correctly, easier to verify, and leaves more chip area for the application-specific accelerators that matter in AI hardware.

RISC-V’s vector extension (RVV 1.0, ratified in 2021) is particularly relevant for AI inference. RVV defines variable-length vector operations — the same type of SIMD (Single Instruction, Multiple Data) operations that are central to efficient matrix multiply implementation — with a design philosophy that allows hardware implementations at different vector lengths to run the same software. A chip designed for low-power edge AI can implement short vectors; a high-performance data center chip can implement long vectors; both run the same RVV-conformant software.

Who Is Actually Shipping RISC-V AI Chips

The narrative that RISC-V is primarily a research or experimental architecture became false around 2022. By 2025, RISC-V processors are shipping in hundreds of millions of devices annually — primarily in microcontrollers, embedded processors, and increasingly in the control processors that manage AI accelerators.

The relevant AI examples:

SiFive’s P550 RISC-V processor has been adopted by Intel’s Pathfinder development program and is a production chip used in AI edge applications. SiFive’s Intelligence X280, a RISC-V processor with extended vector and matrix processing capabilities, targets AI inference at the edge specifically.

Tenstorrent’s Tensix processors — discussed earlier in this series — use RISC-V cores for control and preprocessing, paired with the custom matrix processing fabric for the actual neural network compute. Jim Keller’s choice of RISC-V for the control plane reflects the same reasoning as every other adopter: standardization and freedom from licensing constraints.

Alibaba’s T-Head semiconductor division has designed multiple RISC-V chips for AI applications, including the Xuantie C920, used in Alibaba Cloud’s edge AI products. The C920 includes a matrix multiply extension optimized for transformer inference. Alibaba has open-sourced both the chip design and the toolchain under the Apache 2.0 license, creating a foundation that other Chinese chip designers have built on.

Andes Technology, a Taiwanese company, provides RISC-V IP cores with neural processing extensions to dozens of chip design companies throughout Asia. Their NX27V core, which includes full RISC-V RVV plus a custom machine learning accelerator, has been licensed to chipmakers in Taiwan, South Korea, Japan, and China.

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China’s RISC-V Opportunity

The export control context makes RISC-V’s geopolitical significance clearer. Arm’s technology is subject to UK export control law; since Arm is incorporated in the UK and has substantial operations in the U.S., it must comply with U.S. export regulations when licensing to Chinese companies. Following the 2022 export controls, Arm’s ability to license advanced architecture versions to Chinese customers became uncertain.

RISC-V carries no such restriction. It is a public specification maintained by an international nonprofit. A Chinese company can implement RISC-V silicon with no licensing agreement required and no exposure to U.S. or UK export control for the architecture itself (though U.S.-origin manufacturing equipment and EDA software remain controlled under separate regulations).

This has driven a remarkable surge in Chinese RISC-V development. According to the RISC-V International consortium’s 2023 report, China accounts for approximately 40% of all RISC-V processor shipments globally. The Chinese government’s “Made in China 2025” and its successor industrial policies explicitly identify RISC-V as a strategic technology for semiconductor independence.

The practical limit is that RISC-V freedom from Arm licensing does not solve the foundry problem or the EDA software problem. You can design a RISC-V chip freely, but manufacturing it requires TSMC or SMIC (for advanced nodes) and tools from Cadence, Synopsys, or Mentor — all U.S. companies subject to export controls. The architecture layer is free; the rest of the stack is not.

The Arm Counter-Argument

Arm’s competitive response to RISC-V has been to reduce the friction of Arm licensing while emphasizing the software ecosystem advantage. The Armv9 architecture, released in 2021, included Arm’s own scalable vector extension (SVE2) that competes directly with RISC-V’s RVV for AI workloads. Arm’s Total Design initiative, launched in 2022, provides pre-designed chip subsystems that reduce the time-to-market for Arm-based chips.

The software ecosystem argument is substantial. Android, iOS, Windows for Arm, and essentially every relevant consumer software stack runs on Arm natively. The RISC-V software ecosystem is newer and less complete, particularly for the application software layers that consumer device manufacturers need. An Arm-based smart home device has access to a rich, mature software ecosystem; a RISC-V-based device requires more integration work at every layer.

For custom AI accelerators where the software stack is purpose-built anyway — where you write your own inference runtime, your own compiler backend, your own operator library — the Arm software ecosystem advantage largely disappears. If you are writing all the relevant software from scratch, the choice between Arm and RISC-V for the control processor is primarily a licensing question, and RISC-V has the better answer.

The Open Source Hardware Ecosystem Effect

The most underestimated long-term benefit of RISC-V is not licensing freedom but the open hardware ecosystem it is enabling. Because RISC-V specifications are public and implementations can be freely shared, a growing collection of open-source RISC-V processor designs exists that any chip designer can use as a starting point.

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VexRiscv, PULP Platform’s RI5CY, and Western Digital’s SweRV cores are all open-source RISC-V implementations that have been used as starting points for custom AI chip designs. This is analogous to what Linux did for the operating system ecosystem: not every company needed to write their own kernel from scratch; they could start from a working base and customize.

For startups designing AI inference chips with limited engineering resources, starting from a proven open-source RISC-V control processor rather than licensing an Arm Cortex-M and paying per-chip royalties reduces both time-to-market and marginal unit cost. The difference is meaningful at the margins of viability that many AI chip startups operate near.

RISC-V will not replace Arm in smartphones or PCs on any near-term timeline — the software ecosystem disadvantage is real for those applications. But for the custom AI silicon that is being designed today for edge inference, automotive AI, and industrial applications — where the software stack is custom anyway and licensing freedom has direct economic value — RISC-V is winning market share that is not coming back. The open architecture moment in AI chips is real, and it is happening below the level of visibility that most AI commentary reaches.