In October 2022, the Biden administration imposed sweeping export controls on advanced semiconductor manufacturing equipment to China, effectively preventing TSMC, Samsung, and every other supplier of advanced lithography equipment from shipping to Chinese chipmakers. The policy was designed by Jake Sullivan, the National Security Advisor, and implemented through the Bureau of Industry and Security. It was arguably the most significant industrial policy action by any Western government since the technology export controls of the Cold War era.

The policy made sense only if you understand that TSMC and Samsung Foundry are not just chip manufacturers. They are the physical infrastructure layer of the entire AI stack. Whoever controls advanced chip manufacturing controls who can build capable AI hardware. The U.S. government, in 2022, made a bet that it could use export controls to slow Chinese AI development by bottlenecking it at the foundry layer. Whether that bet succeeds is one of the most consequential open questions in technology geopolitics.

What Foundries Actually Are

The semiconductor industry bifurcated in the 1990s between “fabless” chip designers (who design chips but do not manufacture them) and “foundries” (who manufacture chips but do not design them, selling manufacturing capacity to fabless designers). TSMC, founded by Morris Chang in 1987, pioneered the pure-play foundry model. Samsung Foundry spun out of Samsung’s integrated device manufacturer structure to compete directly.

The economics of advanced chip manufacturing are brutal. A single leading-edge chip fabrication plant (a “fab”) costs $20-30 billion to build and equip. The primary equipment — extreme ultraviolet (EUV) lithography machines from ASML — costs $350 million each, requires specialized support infrastructure, and must be maintained by ASML engineers. A leading-edge fab needs 5-20 EUV machines. The capital requirements are beyond any but the largest corporations or national governments.

TSMC’s competitive advantage is not just capital. It is the accumulated process knowledge from decades of manufacturing optimizations — the specific cleaning recipes, the layer deposition parameters, the defect detection and correction methods — that collectively determine whether a chip manufactured on a given process actually performs as designed. This knowledge is embedded in tens of thousands of engineering decisions made over decades. It cannot be replicated by buying the same equipment, which is why Samsung Foundry, despite having comparable equipment and capital, consistently produces chips with lower yields and worse power efficiency than TSMC on the same nominal process node.

The 3nm Race and What It Actually Means

In September 2022, TSMC began volume production on its N3 process — what the industry calls “3 nanometer” — for Apple’s A16 Bionic chip. Samsung Foundry had announced its 3nm GAA (Gate-All-Around) process earlier in 2022, using a transistor architecture (GAA nanosheet FETs) that is technically more advanced than TSMC’s 3nm FinFET design.

The semiconductor press coverage of this race was largely about the node name: who gets to “3nm” first. This framing is misleading. Node names have been marketing labels rather than physical dimensions since approximately the 14nm generation. TSMC’s “3nm” transistors have a gate pitch of approximately 48nm; Samsung’s “3nm” transistors have similar physical dimensions. What matters is not the name but the actual performance, density, and yield.

On these metrics, TSMC’s N3 process consistently outperforms Samsung Foundry’s 3nm in the chips that customers have designed for each process. Apple’s M3 chip, manufactured on TSMC N3, achieves better power efficiency and performance than any Samsung 3nm product that has shipped. Qualcomm, which historically split orders between TSMC and Samsung Foundry, moved the Snapdragon 8 Gen 3 entirely to TSMC after yield and performance problems with Samsung’s 4nm process in the 8 Gen 1.

This matters for AI hardware because every important AI chip — Nvidia H100, Google TPU v5, Apple M4, AMD MI300 — is manufactured on TSMC’s advanced nodes. Samsung Foundry’s 3nm process, despite its architectural advances, has not won a major AI chip customer for leading-edge production. The AI hardware industry is, for practical purposes, a TSMC industry.

The Taiwan Concentration Risk

TSMC’s Hsinchu Science Park fabs in northern Taiwan manufacture roughly 90% of the world’s most advanced semiconductor chips. This geographic concentration is the single most discussed risk in the semiconductor industry, and also possibly the most misunderstood.

The risk is not simply “what if China invades Taiwan.” The risk is more immediate: a major earthquake in northern Taiwan (which is geologically active — the 1999 Chi-Chi earthquake caused significant damage), a prolonged drought affecting the water supply TSMC’s fabs require (chip manufacturing is extraordinarily water-intensive — a single fab uses 10-50 million gallons of ultra-pure water per day), or severe labor disruption could interrupt production for months. The global supply chain for advanced chips has essentially no buffer.

TSMC has been aggressively diversifying production geography since 2020, driven partly by U.S. government incentives and partly by customers (particularly Apple and Nvidia) pushing for supply chain resilience. TSMC Arizona, announced in 2020 and expanded in 2022, will eventually produce chips on N3 equivalent processes. TSMC Japan, built in partnership with Sony and Denso, opened in early 2024 for automotive and industrial chips. TSMC Germany, announced in 2023 in partnership with Infineon, NXP, and Bosch, targets automotive semiconductor production.

But the Arizona fab timeline has slipped repeatedly. N3 production at TSMC Arizona is not expected before 2028 at the earliest. The production cost at Arizona is estimated at 30-50% higher than at Hsinchu due to higher labor costs, construction costs, and operational overhead. For cost-sensitive customers, Taiwan will remain the primary manufacturing location for years.

Samsung’s Bet on Advanced Packaging

Where Samsung is building a credible competitive position is in advanced packaging — the technology for integrating multiple chips into a single package with high-bandwidth connections between them. Samsung’s I-Cube and Foveros-equivalent packaging technologies compete with TSMC’s CoWoS and Intel’s Foveros for the packaging contracts that accompany HBM and advanced chip integration.

Advanced packaging is critically important for AI hardware because the chips that need to be co-packaged with HBM memory (Nvidia’s H100, AMD’s MI300) require the most sophisticated packaging technology available. TSMC’s CoWoS (Chip on Wafer on Substrate) packaging was a bottleneck for H100 production in 2023 — TSMC could not produce CoWoS packages fast enough to keep up with H100 demand, even though the chip fabrication itself was meeting schedule.

Samsung has invested heavily in packaging capacity since 2023, and there is a plausible scenario where Samsung Foundry captures packaging market share even as it lags in leading-edge chip fabrication. The packaging constraints that have limited AI chip supply are a persistent structural issue; any company that reliably expands packaging capacity captures real revenue.

Intel’s Foundry Ambitions and Why They Matter

Intel’s transformation into a chip foundry (Intel Foundry Services, or IFS) under CEO Pat Gelsinger represents the first serious Western challenge to the TSMC/Samsung duopoly in leading-edge manufacturing. The strategic case is clear: the U.S. government wants domestic chip manufacturing capability for national security reasons, and Intel is the only U.S. company with the history, talent base, and manufacturing facilities to potentially deliver it.

Intel 18A, expected in production in 2025-2026, is Intel’s attempt to leapfrog TSMC N3 using two architectural innovations simultaneously: RibbonFET (a GAA transistor architecture similar to Samsung’s) and PowerVia (backside power delivery, which Intel developed first among the major foundries). If Intel 18A delivers on its technical promises, it would represent the first time an Intel manufacturing process has been competitive with TSMC in over a decade.

The skepticism is warranted: Intel has missed process node deadlines repeatedly since 2018, and the 10nm/7nm naming confusion (Intel’s “10nm” was roughly equivalent to TSMC’s 7nm) eroded confidence. But the strategic incentives for Intel 18A to succeed are enormous — not just for Intel’s business, but for U.S. industrial policy. The $52 billion CHIPS Act allocation assumes that Intel can become a credible advanced foundry by 2027. If it cannot, that assumption requires revision.

China’s Parallel Track

The export control strategy that the U.S. implemented in 2022 has forced Chinese companies to pursue a parallel track: manufacturing advanced chips on processes behind the technology frontier using Chinese-made equipment rather than ASML’s EUV tools.

SMIC, China’s leading foundry, produced Huawei’s Kirin 9000s chip on a 7nm-equivalent process in 2023 using deep ultraviolet (DUV) lithography rather than EUV — a remarkable engineering achievement given the constraints. The yield is reportedly lower than TSMC’s equivalent process, and the power efficiency is worse, but the chip exists and it works. Huawei shipped millions of Mate 60 Pro phones with this chip, demonstrating that U.S. export controls have slowed but not stopped Chinese advanced chip development.

The timeline compression has been remarkable: the goal of Chinese industrial policy under the “Made in China 2025” initiative was semiconductor independence by 2025. That timeline is unrealistic for leading-edge chips. But the 2022 export controls may have paradoxically accelerated China’s domestic capability development by removing any ambiguity about whether the U.S. would ever supply advanced equipment voluntarily. The answer is definitively no. That clarity has focused Chinese investment.

The foundry duopoly’s grip on AI hardware — and by extension, on AI capability itself — is not permanent. But the timeline for meaningful change is measured in decades, not years, and the geopolitical forces shaping that change are already in motion in ways that most technology commentary treats as background noise rather than first-order constraints.

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