Photonic Chips: The Light-Speed Compute Bet and Why It's Harder Than It Sounds

The elevator pitch for photonic computing is almost irresistible: light travels faster than electrons, carries more information per second, generates no resistive heating, and performs certain mathematical operations — specifically matrix multiplication — at the speed of light with near-zero energy. Since matrix multiplication is essentially the only thing that happens inside a transformer neural network, you could be forgiven for concluding that the future of AI hardware is obvious. Swap electrons for photons and you win.

The engineers who have spent the last decade trying to build photonic AI chips will tell you the reality is considerably more complicated. The elevator pitch is not wrong, exactly, but it describes about twenty percent of the actual engineering problem. The other eighty percent is where most photonic startups have broken against the laws of physics in ways that venture capital brochures tend to underemphasize.

The Optical Matrix Multiply: What Actually Works

The core physical insight behind photonic AI accelerators is the Mach-Zehnder interferometer, or MZI. In a standard silicon photonic waveguide, you can split a light beam, phase-shift one path, and recombine — the output intensity depends on the interference between the two paths, which is controlled by the phase shift. Apply a voltage to a modulator and you control the phase; vary that voltage and you implement a continuous-valued weight. Chain multiple MZIs together in a mesh network and you implement a matrix-vector multiplication using the physics of light interference rather than the physics of transistor switching.

This is not a theoretical proposal. It has been demonstrated experimentally many times. The first compelling paper came from MIT in 2017, when Marin Soljačić’s group showed that an MZI mesh could perform matrix multiplication with arbitrarily low energy per operation in principle — the photons propagate through the waveguides without dissipating energy the way electrons dissipate energy as heat through resistance. Lightmatter, Luminous Computing, and Lightelligence all commercialized variations of this architecture through the early 2020s.

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The Lightmatter Passage chip, shipped to selected customers in 2022, demonstrated roughly 100 teraops per watt of efficiency for specific inference workloads — an order of magnitude better than the H100’s approximately 8 teraops per watt on the same metric. That number is real. But understanding what it includes and excludes reveals the hard part.

The Optical-Electronic Interface Problem

Every photonic chip exists in a world of electronic systems. Your data comes from DRAM (electronic). The model weights must be loaded (electronic). The output must be stored and read (electronic). The activations between layers — the outputs of one matrix multiplication that become the inputs to the next — must be converted from the optical domain back to the electronic domain for the nonlinear activation function, then converted back to optical for the next layer.

This optical-to-electrical-to-optical conversion, called O-E-O conversion, consumes energy and time that erase a significant fraction of the optical compute advantage. Each conversion requires a photodetector (which generates heat), an analog-to-digital converter (which consumes power), and a digital-to-analog converter and modulator for the return path. The actual system efficiency, accounting for all conversions in a multi-layer network, is nowhere near the impressive chip-only figure.

Lightmatter’s own published system benchmarks, rather than chip benchmarks, show roughly 5-10x efficiency advantage over equivalent GPU hardware for specific workloads — still significant, but a far cry from the headline numbers. And this assumes that the optical compute is fast enough to keep the conversions from becoming the bottleneck, which requires the optical matrix multiplication to be performed in far less time than the conversion process. For large matrix dimensions, this works. For small batch sizes common in inference, it often does not.

Precision: The Analog Computing Problem Returns

There is a deeper issue with photonic matrix multiplication that the field has known about since the 1980s, when analog optical computing last had its moment of enthusiasm. Analog computation — whether optical or electronic — is inherently noisy. The precision of a photonic matrix multiply is limited by fabrication imperfections, thermal fluctuations in the waveguides, and the signal-to-noise ratio of the optical components.

In practice, photonic MZI meshes achieve roughly 6-8 bits of effective precision under realistic operating conditions. This is comparable to INT8 quantization — workable for many inference tasks, problematic for others, and fundamentally limited by physics rather than engineering effort. You cannot simply add more transistors to get more precision; you would need fundamentally lower-noise optical components, which means colder operating temperatures or more expensive fabrication.

This matters because the transformer architectures dominating AI inference were designed for floating-point precision and are being pushed toward INT8. Pushing further to 6-bit analog computation introduces accuracy degradations that need to be compensated through training techniques, which adds complexity to an already complicated deployment pipeline.

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What MIT Lincoln Laboratory and Analog Photonics Proved

The most important advance in silicon photonic AI chips in the last three years came not from a startup but from MIT Lincoln Laboratory’s collaboration with Analog Photonics, a MIT spin-off. Their 2024 paper in Nature Photonics demonstrated a photonic chip that addressed the precision problem through a calibration approach borrowed from interferometric metrology: rather than building higher-quality waveguides, they continuously measured and corrected the errors.

The chip used on-chip monitors at each MZI junction to measure the actual optical power, compared it to the target, and applied real-time corrections through feedback control loops. The correction overhead consumed power and added latency, but the net result was 8-bit effective precision at a system efficiency of 12 teraops per watt — better than the best uncorrected designs, and done at room temperature with standard CMOS-compatible fabrication.

The limitation is that the feedback loop scales poorly. You need one feedback controller per MZI element, and large matrix meshes contain thousands of MZIs. The overhead scales linearly with matrix size, meaning the efficiency advantage shrinks as you try to implement the large matrices that characterize frontier AI models. Small matrices, small model layers: photonics wins convincingly. The attention mechanism in a 70B parameter transformer: the math gets uncomfortable.

Passage to the Interconnect Future

Where photonics is winning without controversy — and where it is already deployed at scale — is in chip-to-chip and chip-to-memory interconnects. This is a quieter story than the compute headlines, but possibly a more important one.

Intel’s co-packaged optics program, Broadcom’s photonics division, and startups like Ayar Labs are shipping or near-shipping optical I/O chiplets that attach directly to compute chips, replacing copper electrical traces with optical fiber at the package level. A 64-lane optical I/O chiplet from Ayar Labs delivers 4 terabits per second of bandwidth in under 1 watt, compared to roughly 400 gigabits per second for equivalent electrical interfaces consuming 15 watts.

This bandwidth advantage, at an order-of-magnitude power advantage, solves the memory wall problem for AI chips in a way that does not require an entire photonic compute revolution. If you can move weights from memory to compute at 4 Tb/s, the arithmetic intensity constraint relaxes substantially. Nvidia has been investing in silicon photonics research for exactly this reason — not to replace the GPU with optical compute, but to eliminate the interconnect bottleneck that limits how fast weights can be fed to the GPU’s matrix units.

Ayar Labs was acquired by Nvidia in January 2025 for approximately $1.2 billion, which tells you exactly where Nvidia thinks the photonics value is concentrated.

The Timeline for Optical Compute

The honest commercial timeline for photonic AI compute accelerators — chips where the matrix multiplication itself happens in optical domain — is a decade or more for frontier model inference, and three to five years for edge inference tasks on smaller models. The edge case is more tractable because it involves smaller matrices, lower precision requirements, and scenarios where the power advantage justifies the deployment complexity.

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Lightmatter’s Envise platform, targeting data center inference, will find commercial customers among hyperscalers who are sophisticated enough to build the integration infrastructure and care enough about power bills to invest in new tooling. But it will not displace GPUs at scale this decade.

The optical interconnect story is different: it is already happening, the economics are compelling, and the engineering challenges are solved. By 2028, a significant fraction of high-bandwidth memory connections in data center AI chips will be optical. This is not a breakthrough — it is an engineering transition that is already underway, driven by the same physics that makes photonic compute interesting, applied to a problem where the engineering is more tractable.

The light-speed compute bet is real. The timeline is being written by physics, not by venture capital enthusiasm.